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PRELIMINARY DATA SHEET
256MB Unbuffered DDR2 SDRAM HYPER DIMM
EBE25UC8AAFV (32M words x 64 bits, 1 Rank)
Description
The EBE25UC8AAFV is 32M words x 64 bits, 1 rank DDR2 SDRAM unbuffered module, mounting 8 pieces of 256M bits DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA on the module board. Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects.
Features
* 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free * 1.8V power supply * Data rate: 700Mbps/667Mbps/600Mbps (max.) * 1.8V (SSTL_18 compatible) I/O * Double-data-rate architecture: two data transfers per clock cycle * Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver * DQS is edge aligned with data for READs: centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS * Four internal banks for concurrent operation (components) * Data mask (DM) for write data * Burst lengths: 4, 8 * /CAS Latency (CL): 3, 4, 5 * Auto precharge operation for each burst access * Auto refresh and self refresh modes * 7.8s average periodic refresh interval * Posted CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality * /DQS can be disabled for single-ended Data Strobe operation
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Document No. E0527E12 (Ver. 1.2) Date Published February 2006 (K) Japan Printed in Japan URL: http://www.elpida.com
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This product became EOL in April, 2005.
Elpida Memory, Inc. 2004-2006
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EBE25UC8AAFV
Ordering Information
Part number EBE25UC8AAFV-DF-E EBE25UC8AAFV-BE-E EBE25UC8AAFV-AE-E Data rate Mbps (max.) 700 667 600 Component JEDEC speed bin (CL-tRCD-tRP) DDR2-700 (5-6-6) DDR2-667 (5-5-5) DDR2-600 (5-5-5) Package 240-pin DIMM (lead-free) Contact pad Mounted devices EDE2508AASE-DF Gold EDE2508AASE -DF, -BE EDE2508AASE -DF, -BE, -AE
Pin Configurations
Front side 1 pin 64 pin 65 pin 120 pin
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Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2
121 pin Back side
184 pin 185 pin
240 pin
Pin No. 61 62 63
Pin name A4 VDD A2 VDD VSS VSS VDD
Pin No. 121 122 123 124 125 126 127
Pin name VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS
Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193
Pin name VDD A3 A1 VDD CK0 /CK0 VDD A0 VDD BA1 VDD /RAS /CS0 VDD ODT0 NC VDD VSS DQ36
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Pr
NC 128 VDD A10 129 130 BA0 131 VDD /WE 132 133 /CAS VDD NC NC VDD VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
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DM1 NC 194 195 VSS 196 CK1 197 /CK1 198 VSS 199 DQ14 200 DQ15 VSS 201 202 DQ20 203 DQ21 VSS DM2 NC VSS 204 205 206 207 208
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DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS
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DQ44
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EBE25UC8AAFV
Pin No. 29 30 31 32 33 34 35 36 37 38 39 Pin name VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pin name DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 Pin No. 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Pin name DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS NC NC VSS NC NC VSS VDD NC VDD NC NC VDD A12 A9 Pin No. 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 Pin name DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 /CK2 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
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40 41 42 DQ27 VSS NC 43 44 45 NC VSS NC 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 NC VSS NC NC VSS VDD CKE0 VDD NC NC VDD A11 A7 VDD A5
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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108 109 110 111 112 113 114 115 116 117 118 119 120
Pr
VSS 172 /DQS7 DQS7 VSS 173 174 175 DQ58 176 DQ59 VSS SDA SCL 177 178 179 180
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VDD A8 238 239 A6 240
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3
EBE25UC8AAFV
Pin Description
Pin name A0 to A12 A10 (AP) BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0 Function Address input Row address Column address Auto precharge Bank select address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground A0 to A12 A0 to A9
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CKE0 CK0 to CK2 /CK0 to /CK2 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0 NC
DQS0 to DQS7, /DQS0 to /DQS7
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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ODT control No connection
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EBE25UC8AAFV
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Bit4 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 Bit3 0 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 Bit2 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 Bit1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 Bit0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Hex value 80H 08H 08H 0DH 0AH 60H 40H 00H 05H 3DH 50H 00H 82H 08H 00H 00H 0CH 04H 38H 00H 02H 00H 30H 3DH 50H Comments 128 bytes 256 bytes DDR2 SDRAM 13 10 1 64 0 SSTL 1.8V 3.75ns* 0.5ns* None. 7.8s x8 None. 0 4,8 4 3, 4, 5 0 Unbuffered Normal VDD 0.1V 3.75ns* 0.5ns* 5.0ns* 0.6ns* 15ns 7.5ns 15ns
1 1 1 1
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Reserved Reserved
Voltage interface level of this assembly 0 0 0 0 1 0 0 0 0 0 0 0
DDR SDRAM cycle time, CL = 5 SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency DIMM type information
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 4
Maximum data access time (tAC) from 0 clock at CL = 4 Minimum clock cycle time at CL = 3 0 Maximum data access time (tAC) from 0 clock at CL = 3 Minimum row precharge time (tRP) Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) Module rank density 0 0 0 0 0
Address and command setup time 0 before clock (tIS) Address and command hold time after 0 clock (tIH) Data input setup time before clock 0 (tDS) Data input hold time after clock (tDH) 0
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0
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0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1
50H 60H
1
1
3CH 1EH
3CH
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2DH 45ns 40H 256M bytes 0.25ns* 0.38ns* 0.10ns*
1
25H 38H 10H
1
t
1
23H
0.23ns*
1
5
EBE25UC8AAFV
Byte No. 36 37 38 39 40 41 42 43 44 45
Function described Write recovery time (tWR) Internal write to read command delay (tWTR) Internal read to precharge command delay (tRTP) Extension of Byte 41 and 42 Active command period (tRC) Auto refresh to active/ Auto refresh command cycle (tRFC) SDRAM tCK cycle max. (tCK max.) Dout to DQS skew
Bit7 0 0 0
Bit6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 x 1 1 1
Bit5 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 x 0 0 0
Bit4 1 1 1 0 0 1 0 0 1 0 0 0 1 0 1 1 0 x 0 0 0
Bit3 1 1 1 0 0 1 1 0 1 1 0 0 0 0 1 1 0 x 0 0 0
Bit2 1 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1 0 x 1 0 1 0 1 1 0 0
Bit1 0 1 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 x 0 1 0 1 0 0 1 0
Bit0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 x 1 0 1 0 1 1 1 0
Hex value 3CH 1EH 1EH 00H 00H 3CH 4BH 80H 1EH 28H 00H 00H 10H 82H 7FH FEH 00H xx 45H 42H 45H 32H 35H 55H 43H 38H 41H 41H
Comments 15ns*
1
7.5ns* 7.5ns* TBD
1
1
Memory analysis probe characteristics 0 0 0 0 1 0 0 0 0 0 1 0 1 0 x 0 0 0
Undefined 60ns* 75ns* 8ns*
1 1 1 1
1
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46 PLL relock time 47 to 61 62 SPD Revision 63 64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 -BE -AE 87 -BE -AE 88
0.30ns* 0.40ns*
Data hold skew (tQHS)
Undefined
Rev. 1.0 Continuation code Elpida Memory (ASCII-8bit code) E B E 2 5 U C 8 A A F V -- D B A
Checksum for bytes 0 to 62
Manufacturer's JEDEC ID code
Manufacturer's JEDEC ID code
Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -DF
Module part number -DF
Module part number
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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Pr
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
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0 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1
46H 56H
2DH 44H
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42H 41H 46H F 45H E 45H E
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--
2DH
6
EBE25UC8AAFV
Byte No. 89 90 91 92 93 94 95 to 98 99 to 127
Function described Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacture specific data
Bit7 0 0 0 0 x x
Bit6 1 0 0 0 x x
Bit5 0 1 1 1 x x
Bit4 0 0 1 0 x x
Bit3 0 0 0 0 x x
Bit2 1 0 0 0 x x
Bit1 0 0 0 0 x x
Bit0 1 0 0 0 x x
Hex value 45H 20H 30H 20H xx xx
Comments E (Space) Initial (Space) Year code (BCD) Week code (BCD)
Note: These specifications are defined based on component specification, not module.
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Preliminary Data Sheet E0527E12 (Ver. 1.2)
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EBE25UC8AAFV
Block Diagram
/CS0 RS1 /DQS0 RS1 DQS0 RS1 DM0 8 DQ0 to DQ7 RS1 DM /CS DQS /DQS DQS4 RS1 DM4 8 DQ32 to DQ39 RS1 DM /CS DQS /DQS /DQS4 RS1 RS1
DQ0 to DQ7
D0
DQ0 to DQ7
D4
RS1 /DQS1 RS1 DQS5 /CS DQS /DQS DM DQ0 to DQ7 /DQS5
RS1 RS1 RS1 DM5 8 DQ40 to DQ47 RS1 DM DQ0 to DQ7 /CS DQS /DQS
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DQS1 DM1 8 DQ8 to DQ15 /DQS2 DQS2 DM2 DQ16 to DQ23 8 /DQS3 DQS3 DM3 8 DQ24 to DQ31 BA0 to BA1 A0 to A12 /RAS /CAS /WE CKE0 ODT0 VDDSPD VREF VDD VSS Rs1 : 22 Rs2 : 5.1
RS1 RS1
D1
D5
RS1 /DQS6 RS1 DQS6 /CS DQS /DQS DM6 8 DQ48 to DQ55
RS1 RS1 RS1 DM RS1 DQ0 to DQ7 /CS DQS /DQS
RS1 RS1
* D0 to D7 : 256M bits DDR2 SDRAM U0 : 2k bits EEPROM
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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DM DQ0 to DQ7 RS1 RS1 RS1 RS1 DM DQ0 to DQ7
RS2 RS2 RS2 RS2 RS2
D2
D6
RS1 /DQS7
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/CS DQS /DQS
RS1 /CS DQS /DQS DM 8 RS1 DQ0 to DQ7
DQS7 RS1
DM7
D3
DQ56 to DQ63
D7
BA0 to BA1: SDRAMs (D0 to D7) A0 to A12: SDRAMs (D0 to D7) /RAS: SDRAMs (D0 to D7) /CAS: SDRAMs (D0 to D7) /WE: SDRAMs (D0 to D7)
CKE: SDRAMs (D0 to D7) ODT:SDRAMs (D0 to D7)
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Serial PD SCL SA0 SA1 SA2 SCL A0
SDA
SDA
U0
A1 A2
WP
Notes :
1. DQ wiring maybe changed within a byte. must be meintained as shown.
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7) 3. Refer to the appropriate clock wiring topology
under the DIMM wiring details section of this document.
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SDRAMs (D0 to D7)
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EBE25UC8AAFV
Logical Clock Net Structure
3DRAM loads (CK1 and /CK1, CK2 and /CK2)
R = 200
DRAM
C1
DRAM
C1
DIMM connector R = 200
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R = 200
DRAM
C1
2DRAM loads (CK0 and /CK0)
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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DIMM connector
R = 200
DRAM
C1
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R = 200
C2
R = 200
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DRAM C1 * C1: 1pF C2: 2pF
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EBE25UC8AAFV
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol VT VDD IOS PD TC Tstg Value -0.5 to +2.3 -0.5 to +2.3 50 8 0 to +85 -55 to +100 Unit V V mA W C C 1 Note
Note: DDR2 SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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Parameter Supply voltage Input reference voltage Termination voltage DC input logic high DC input low AC input logic high AC input low
DC Operating Conditions (TC = 0 to +85C) (DDR2 SDRAM Component Specification)
Symbol VDD, VDDQ VSS VDDSPD min. 1.8 0 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 VREF + 0.250 typ. 1.85 0 -- VREF max. 1.9 0 3.6 VREF + 0.04 VDDQ + 0.3V VREF - 0.125 VREF - 0.250 Unit V V V V V V V V V 1, 2 3 Notes 4
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ must be equal to VDD.
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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VREF VTT VIH (DC) VIL (DC) VIL (AC) VIH (AC)
0.50 x VDDQ 0.51 x VDDQ
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10
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EBE25UC8AAFV
DC Characteristics 1 (TC = 0 to +85C, VDD = 1.85V 0.05V, VSS = 0V)
Parameter Operating current (ACT-PRE) Symbol Grade -DF IDD0 -BE -AE -DF Operating current (ACT-READ-PRE) IDD1 -BE -AE max. 1000 1000 960 1120 1120 1080 96 96 88 240 240 200 320 320 280 360 360 320 240 mA Fast PDN Exit all banks open; MRS(12) = 0 tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Slow PDN Exit Data bus inputs are FLOATING MRS(12) = 1 all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA mA mA mA mA Unit Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
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Precharge power-down standby current Idle standby current Active power-down standby current Active standby current Operating current (Burst read operating) Operating current (Burst write operating)
-DF -BE -AE -DF -BE -AE -DF
IDD2P
Precharge quiet standby IDD2Q current
Preliminary Data Sheet E0527E12 (Ver. 1.2)
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IDD2N -BE -AE -DF IDD3P-F -BE -AE -DF IDD3P-S -BE -AE -DF IDD3N -BE -AE -DF IDD4R -BE -AE -DF IDD4W -BE -AE
Pr
240 200 680 640 600 1840 1760 1680 1840 1760 1680 mA mA mA mA
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11
all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
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EBE25UC8AAFV
Parameter
Symbol
Grade -DF
max. 2160 2160 2080
Unit
Test condition tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self Refresh Mode; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) -1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK (IDD); See Notes 7; CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W;
Auto-refresh current
IDD5
-BE -AE
mA
Self-refresh current
IDD6
48
mA
-DF
2720 2720 2640 mA
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Operating current (Bank interleaving)
IDD7
-BE -AE
Notes: 1. 2. 3. 4.
IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN VIL (AC) (max.) H is defined as VIN VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. 7. In case of -DF (DDR2-700), tRCD must be 2 x tCK (IDD) and AL must be 4 x tCK (IDD) because AL = 5 is not supported in this device.
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR2-700 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD) 5-6-6 5 15 67.5 7.5 2.85 50 70000 15 85 DDR2-667 5-5-5 5 15 60 7.5 3 45 70000 15 75
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
Pr
12
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DDR2-600 5-5-5 5 15 65 7.5 3.3 47.5 70000 15 80
Unit tCK ns
uc
ns ns ns ns ns ns
t
ns
EBE25UC8AAFV
DC Characteristics 2 (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value TBD TBD VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4 Unit A A V V V mA mA Notes VDD VIN VSS VDDQ VOUT VSS 5 5 1 3, 4, 5 2, 4, 5
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
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Notes: 1. 2. 3. 4. 5.
Parameter AC differential input voltage
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18 at TA = 25C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V) (DDR2 SDRAM Component Specification)
AC differential cross point voltage AC differential cross point voltage
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as /CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
VTR VCP
Symbol
min. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125
max. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125
Unit V V V
Notes 1 2 3
VID (AC) VIX (AC) VOX (AC)
Pr
VDDQ
VSSQ
Differential Signal Levels*1, 2
od
VID
Crossing point
VIX or VOX
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EBE25UC8AAFV
ODT DC Electrical Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V) (DDR2 SDRAM Component Specification)
Parameter Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Deviation of VM with respect to VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) VM min. 60 120 -3.75 typ. 75 150 max. 90 180 +3.75 Unit % Notes 1 1 1
Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18.
EO
Parameter Output impedance Output slew rate Parameter Input capacitance Input capacitance Data and DQS input/output capacitance
Rtt(eff) =
VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC))
Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load.
VM =
2 x VM VDDQ
- 1 x 100%
OCD Default Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V) (DDR2 SDRAM Component Specification)
Pull-up and pull-down mismatch
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.
Pin Capacitance (TA = 25C, VDD = 1.85V 0.05V)
Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /CS, CKE, ODT CK, /CK DQ, DQS, /DQS, DM
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
Pr
min. typ. 12.6 18 0 1.5
max. 23.4 4 4.5
Unit V/ns
Notes 1 1, 2 3, 4
od
max. TBD TBD TBD
uc
Unit pF Note pF
t
pF
14
EBE25UC8AAFV
AC Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V, VSS = 0V) (DDR2 SDRAM Component Specification)
-DF Frequency (Mbps) Parameter /CAS latency Active to read or write command delay Precharge command period Symbol CL tRCD tRP 700 min. 5 15 15 max. 5 +450 +400 0.55 0.55 8000 tAC max. -BE 667 min. 5 15 15 60 -450 -400 0.45 0.45 min. (tCL, tCH) 3000 225 100 0.6 0.35 max. 5 +450 +400 0.55 0.55 8000 tAC max. -AE 600 min. 5 15 15 60 -500 -450 0.45 0.45 min. (tCL, tCH) 3300 225 100 0.6 0.35 tAC min. max. 5 +500 +450 0.55 0.55 8000 tAC max. tAC max. 300 400 Unit Notes tCK ns ns ns ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK 5 4
Active to active/auto refresh tRC 60 command time DQ output access time from tAC -450 CK, /CK DQS output access time from tDQSCK -400 CK, /CK CK high-level width CK low-level width CK half period tCH tCL tHP tCK tDH tDS 0.45 0.45 min. (tCL, tCH) 2850 225 100 0.6
EO
Clock cycle time DQ and DM input hold time DQ and DM input setup time DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width Write preamble setup time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble
Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals
DQS falling edge to CK setup tDSS time DQS falling edge hold time tDSH from CK Mode register set command tMRD cycle time tWPST tWPRE tIH tIS tRPRE
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
tIPW tDIPW tHZ tLZ 0.35 tAC min. tDQSQ tQHS tQH tDQSS tDQSH tDQSL WL - 0.25 0.35 0.35 0.2 0.2 2 tWPRES 0 0.4 0.35 250 125 0.9
Pr
tAC max. 300 tAC min. 400 tHP - tQHS WL + 0.25 0.6 1.1 WL - 0.25 0.35 0.35 0.2 0.2 2 0 0.4 0.35 250 125 0.9
tAC max. 300 400
tHP - tQHS
tHP - tQHS WL - 0.25 WL + 0.25 1.1
od
WL + 0.25 0.6 1.1 0.35 0.35 0.2 0.2 2 0 0.4 0.35 375 250 0.9
uc
0.6 tCK tCK ps ps 5 4
t
tCK
15
EBE25UC8AAFV
-DF Frequency (Mbps) Parameter Read postamble Active to auto-precharge delay Active bank A to active bank B command period Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay Auto refresh to active/auto refresh command time Average periodic refresh interval Minimum time clocks remains ON after CKE asynchronously drops low Symbol tRPST 700 min. 0.4 45 tRCD min. 7.5 15 max. 0.6 70000 -BE 667 min. 0.4 45 tRCD min. 7.5 15 max. 0.6 70000 -AE 600 min. 0.4 45 tRCD min. 7.5 15 max. 0.6 70000 Unit Notes tCK ns ns ns ns tCK ns ns ns tCK tCK tCK tCK tCK ns ns s ns 3 2, 3 1
Active to precharge command tRAS tRAP tRRD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD
(tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 12
(tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 0 12
(tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 0 75 12 7.8
EO
Notes: 1. 2. 3. 4.
DQS /DQS tDS
For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
tCKE tOIT tRFC tREFI 3 0 75 tDELAY
tDH tDS tDH
tXARDS 6 - AL
Input Waveform Timing 1 (tDS, tDH)
Pr
75 7.8 tIS + tCK + tIH
CK /CK tIS
7.8
tIS + tCK + tIH
tIS + tCK + tIH
VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
od
tIH tIS tIH
Input Waveform Timing 2 (tIS, tIH)
uc
VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
t
16
EBE25UC8AAFV
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter ODT turn-on delay ODT turn-on ODT turn-on (power down mode) ODT turn-off delay ODT turn-off ODT turn-off (power down mode) ODT to power down entry latency ODT power down exit latency Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min. 2 tAC(min) tAC(min) + 2000 2.5 tAC(min) tAC(min) + 2000 3 8 max. 2 tAC(max) + 1000 2tCK + tAC(max) + 1000 2.5 tAC(max) + 600 2.5tCK + tAC(max) + 1000 3 8 Unit tCK ps ps tCK ps ns tCK tCK 2 1 Notes
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
EO
Parameter Input reference voltage
AC Input Test Conditions
Symbol VREF VSWING(max.) SLEW Value 0.5 x VDDQ 1.0 1.0 Unit V V V/ns Notes 1 1 2, 3
Input signal maximum peak to peak swing Input signal maximum slew rate
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
VSWING(max.) TF Falling slew =
Start of falling edge input timing
VIH (DC)(min.) - VIL (AC)(max.) TF
Pr
TR
Start of rising edge input timing
VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF
AC Input Test Signal Wave forms
Measurement point
DQ RT =25
Output Load
od
VSS
Rising slew = TR
VIL (DC)(max.) VIL (AC)(max.)
VIH (AC) min. - VIL (DC)(max.)
uc t
VTT
17
EBE25UC8AAFV
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)
EO
Bank 0 Bank 1 Bank 2 Bank 3
[Bank Select Signal Table]
Remark: H: VIH. L: VIL.
CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.
DQ (input and output pins) Data are input to and output from these pins.
DQS and /DQS (input and output pin) DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
L H L H
Pr
BA0
BA1 L L
od
H H
uc
t
18
EBE25UC8AAFV
DM (input pins) DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS. VDD (power supply pins) 1.8V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 1.8V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected.
EO
Detailed Operation Part and Timing Waveforms
Refer to the EDE2508AASE-DF, -BE, -AE, EDE2516AASE-DF, -BE, -AE datasheet (E0515E).
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L Pr od uc t
19
EBE25UC8AAFV
Physical Outline
Unit: mm
4.00 max (DATUM -A-)
0.5 min
Component area (Front)
1 120
B 63.00 133.35 55.00
A 1.27 0.10
240
10.00
121
17.80
4.00 min
Component area (Back)
3.00
4.00
FULL R
Detail A
2.50 0.20
Detail B
1.00
(DATUM -A-)
4.00
0.20 0.15
2.50
FULL R
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
30.00
EO
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
Pr
20
od uc t
EBE25UC8AAFV
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
EO
1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
Pr
21
od
uc
CME0107
t
EBE25UC8AAFV
HYPER DIMM is a trademark of Elpida Memory, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.
EO
[Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
Preliminary Data Sheet E0527E12 (Ver. 1.2)
L
Pr
22
od
M01E0107
uc t

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